The present invention generally relates to semiconductor transistor devices, and more specifically, to fabrication methods and resulting structures for non-self-aligned gate contacts formed over the active region of a transistor.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit (IC) having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. The channel region connects the source and the drain. Electrical current is induced to flow through the channel region from the source to the drain by a voltage applied at the gate electrode.
IC structures have middle of the line (MOL) contacts that connect the semiconductor devices to back end of the line (BEOL) metal levels. For example, a MOSFET can have a gate contact (also referred to herein as a CB contact) and source/drain contacts (also referred to herein as CA contacts). The gate contact can extend vertically through an interlayer dielectric (ILD) material of the IC from a metal wire or via in the first back end of the line (BEOL) metal level (referred to herein as MO) to the gate of the MOSFET. The source/drain contacts can extend vertically through the ILD material from metal wires or vias in the BEOL metal level to metal plugs (also referred to herein as TS contacts), which are on the source/drain regions of the MOSFET. Historically, in order to avoid shorts between the gate contact and the metal plugs, the gate contact is formed on a portion of the gate that is offset from the active region of the FET and, more particularly, on a portion of the gate that extends laterally over the adjacent isolation region. However, given the ever present need for size scaling of devices, methods have been developed that allow for a gate contact to be formed on a portion of the gate directly above the active region (referred to herein as a CB-over-active or CBoA) or close thereto, but ensures that the risk of a short developing between the gate contact and any of the metal plugs is avoided (or at least significantly reduced).